1. Field of the Invention
The present invention relates generally to the field of complementary symmetry MOS (CMOS) logic circuits and, more specifically, to an output buffer for converting CMOS logic signals to their equivalent emitter-coupled logic (ECL) voltage levels.
2. Background of the Invention
A CMOS circuit's logic level "1" approaches the power supply value which is generally three to five volts, while its logic level "0" is near the reference or ground level. On the other hand, an ECL circuit's logic level "1" is generally about -0.8 volts while its logic level "0" is generally about -1.68 volts. Therefore, some form of interface or buffer circuit must receive CMOS level signals and convert them to ECL level signals if CMOS logic is to communicate with ECL logic.
Such an interface or buffer circuit should contain only a few transistors. A circuit with few transistors minimizes the use of silicon area and minimizes propagation delays attributable to the circuit. The interface circuit should also maintain a relatively constant low output-impedance during the circuit's transition from one logic state to another. Further, correct ECL logic levels must be generated by the buffer despite variations in the CMOS process employed to make the buffer, variations in power supply voltages, and other variations such as changes in operating temperature.
A known buffer for converting CMOS logic levels to their corresponding ECL logic levels comprises transistors of opposite conductivity types and a saturation means responsive to a signal on an input terminal. This saturation means saturates a transistor in an "ON" state when the logic level "0" is applied to the input terminal. However, this known buffer circuit requires non-standard-voltage power supplies for operation.
It would therefore be advantageous to provide a buffer circuit that operates satisfactorily on standard CMOS and ECL power supply voltages. As used herein, the term "bilingual" refers to a capability of a circuit that converts one logic level (e.g., CMOS) to another logic level (e.g., ECL) using standard biasing voltages on the same substrate. Such a buffer should change state quickly to minimize propagation delays attributable to the buffer. It would further be advantageous to provide a CMOS to ECL buffer that provides reliable ECL signal voltage levels despite variations in the CMOS process, power supply voltages, and operating temperature.